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ST95040 ST95020, ST95010
4K/2K/1K Serial SPI EEPROM with Positive Clock Strobe
1 MILLION ERASE/WRITE CYCLES 40 YEARS DATA RETENTION SINGLE SUPPLY VOLTAGE - 4.5V to 5.5V for ST950x0 - 2.5V to 5.5V for ST950x0W SPI BUS COMPATIBLE SERIAL INTERFACE 2 MHz CLOCK RATE MAX BLOCK WRITE PROTECTION STATUS REGISTER 16 BYTE PAGE MODE WRITE PROTECT SELF-TIMED PROGRAMMING CYCLE E.S.D.PROTECTION GREATER than 4000V SUPPORTS POSITIVE CLOCK SPI MODES
8 1
PSDIP8 (B) 0.25mm Frame
8 1
SO8 (M) 150mil Width
Figure 1. Logic Diagram DESCRIPTION The ST950x0 is a family of Electrically Erasable Programmable Memories (EEPROM) fabricated with STMicroelectronics's High Endurance Single Polysilicon CMOS technology. Each memory is accessed by a simple SPI bus compatible serial interface. The bus signals are a serial clock input (C), a serial data input (D) and a serial data output (Q).
VCC
D C
Q
Table 1. Signal Names
C D Q S W HOLD VCC VSS Serial Clock Serial Data Input Serial Data Output Chip Select Write Protect Hold Supply Voltage Ground
S W HOLD
ST950x0
VSS
AI01435B
June 1998
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ST95040, ST95020, ST95010
Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections
ST950x0 S Q W VSS 1 2 3 4 8 7 6 5
AI01436B
ST950x0 VCC HOLD C D S Q W VSS 1 2 3 4 8 7 6 5
AI01437B
VCC HOLD C D
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TLEAD VO VI VCC VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature, Soldering Output Voltage Input Voltage with respect to Ground Supply Voltage Electrostatic Discharge Voltage (Human Body model) (2) Electrostatic Discharge Voltage (Machine model)
(3)
Value -40 to 125 -65 to 150
Unit C C C V V V V V
(SO8 package) (PSDIP8 package)
40 sec 10 sec
215 260 -0.3 to VCC +0.6 -0.3 to 6.5 -0.3 to 6.5 4000 500
Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not i mplied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100pF, 1500) 3. EIAJ IC-121 (Condition C) (200pF, 0)
DESCRIPTION (cont'd) The device connected to the bus is selected when the chip select input (S) goes low. Communications with the chip can be interrupted with a hold input (HOLD). The write operation is disabled by a write protect input (W). Data is clocked in during the low to high transition of clock C, data is clocked out during the high to low transition of clock C.
SIGNALS DESCRIPTION Serial Output (Q). The output pin is used to transfer data serially out of the Memory. Data is shifted out on the falling edge of the serial clock. Serial Input (D). The input pin is used to transfer data serially into the device. It receivesinstructions, addresses, and the data to be written. Input is latched on the rising edge of the serial clock.
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ST95040, ST95020, ST95010
Figure 3. Data and Clock Timing
CPOL CPHA
0
0
C
1
1
C
D or Q
MSB
LSB
AI01438
Figure 4. Microcontroller and SPI Interface Set-up
MICROCONTROLLER (ST6, ST7, ST9, ST10, OTHERS)
SCK SPI Interface with (CPOL, CPHA) = ('0', '0') or ('1', '1') SDI SDO
C Q D
ST95xx0
AI01439B
Serial Clock (C). The serial clock provides the timing of the serial interface. Instructions, addresses, or data present at the input pin are latched on the rising edge of the clock input, while data on the Q pin changes after the falling edge of the clock input. Chip Select (S). When S is high, the Memory is deselected and the Q output pin is at high impedance and, unless an internal write operation is underway the Memory will be in the standby power mode. S low enables the Memory, placing it in the active power mode. It should be noted that after
power-on, a high to low transition on S is required prior to the start of any operation. Write Protect (W). This pin is for hardware write protection. When W is low, writes to the Memory are disabled but any other operationsstay enabled. When W is high, all writes operationsare available. W going low at any time before the last bit D0 of the data streamwill reset the write enable latch and prevent programming. No action on W or on the write enable latch can interrupt a write cycle which has commenced.
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ST95040, ST95020, ST95010
Hold (HOLD). The HOLD pin is used to pause serial communications with the Memory without resetting the serial sequence. To take the Hold condition into account, the product must be selected (S = 0). Then the Hold state is validated by a high to low transition on HOLD when C is low. To resumethe communications,HOLDis broughthigh while C is low. During the Hold condition D, Q, and C are at a high impedance state. When the Memory is under the Hold condition, it is possibleto deselect the device. However, the serial communications will remain paused after a reselect, and the chip will be reset. TheMemorycan bedrivenby a microcontroller with its SPI peripheral running in either of the two following modes: (CPOL, CPHA) = ('0', '0') or (CPOL, CPHA) = ('1', '1'). For these two modes, input data is latchedin by the low to high transition of clock C, and output data is available from the high to low transition of Clock (C). The differencebetween (CPOL, CPHA)= (0, 0) and (CPOL, CPHA) = (1, 1) is the stand-by polarity: C remains at '0' for (CPOL, CPHA) = (0, 0) and C remains at '1'for (CPOL, CPHA) = (1, 1) when there is no data transfer. OPERATIONS All instructions, addresses and data are shifted in and out of the chip MSB first. Data input (D) is sampled on the first rising edge of clock (C) after the chip select (S) goes low. Prior to any operation, a one-byte instruction code must be entered in the chip. This code is entered via the data input (D), and latched on the rising edge of the clock input (C). To enter an instruction code, the product must have been previously selected (S = low). Table 3 shows the instruction set and format for device Table 3. Instruction Set
Instruction WREN WRDI RDSR WRSR READ WRITE Description Set Write Enable Latch Reset Write Enable Latch Read Status Register Write Status Register Read Data from Memory Array Write Data to Memory Array Instruction Format 0000 0110 0000 0100 0000 0101 0000 0001 0000 A8011 0000 A8010
operation. If an invalid instruction is sent (one not contained in Table 3), the chip is automatically deselected. For operations that read or write data in the memory array, bit 3 of the instruction is the MSB of the address, otherwise, it is a don't care. Write Enable (WREN) and Write Disable (WRDI) The Memory contains a write enable latch. This latch must be set prior to every WRITE or WRSR operation. The WREN instruction will set the latch and the WRDI instruction will reset the latch. The latch is reset under the following conditions: - W pin is low - Power on - WRDI instruction executed - WRSR instruction executed - WRITE instruction executed As soon as the WREN or WRDI instruction is received by the memory, the circuit executes the instruction and enters a wait mode until it is deselected. Read Status Register (RDSR) TheRDSR instructionprovidesaccessto the status register. The status register may be read at any time, even during a write to the memory operation. If a Read Status register reaches the 8th bit of the Status register, an additional 9th clock pulse will wrap around to read the 1st bit of the Status Register The status register format is as follows:
b7 1 1 1 1 BP1 BP0 WEL b0 WIP
BP1, BP0: Read and write bits WEL, WIP: Read only bits. b7 to b4: Read only bits.
Notes: A8 = 1, Upper page selected on ST95040. A8 = 0, Lower page selected on ST95040.
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ST95040, ST95020, ST95010
Figure 5. Block Diagram
HOLD W S C D Q Control Logic
High Voltage Generator
I/O Shift Register
Address Register and Counter
Data Register
Status Block Protect
Y Decoder
16 Bytes
X Decoder
AI01272
During a write to the memory operation to the memory array, all bits BP1, BP0, WEL, WIP are valid and can be read. During a write to the status register, only the bits WEL and WIP are valid and can be read. The values of BP1 and BP0 read at that time correspondto the previouscontents of the status register. The Write-In-Process (WIP) read-only bit indicates whether the Memory is busy with a write operation.
When set to a '1' a write is in progress, when set to a '0' no write is in progress. The Write Enable Latch (WEL) read-only bit indicates the status of the write enable latch. When set to a '1' the latch is set, when set to a '0' the latch is reset. The Block Protect (BP0 and BP1) bits indicate the extent of the protection employed. These bits are set by the user issuing the WRSR instruction. These bits are non-volatile.
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ST95040, ST95020, ST95010
Figure 6. Read Operation Sequence
S 0 C INSTRUCTION BYTE ADDRESS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 DATA OUT 7 6 5 4 3 2 1 0
AI01440
HIGH IMPEDANCE Q
Notes:
A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only active on ST95040.
Table 4. Write Protected Block Size
Status Register Bits BP1 0 0 1 1 BP0 0 1 0 1 none Upper quarter Upper half Whole memory Protected Block ST95040 none 180h - 1FFh 100h - 1FFh 000h - 1FFh Array Address Protected ST95020 none C0h - FFh 80h - FFh 00h - FFh ST95010 none 60h - 7Fh 40h - 7Fh 00h - 7Fh
Write Status Register (WRSR) The WRSR instruction allows the user to select the size of protected memory. The user may read the blocks but will be unable to write within the protected blocks. The blocks and respective WRSR control bits are shown in Table 4. When the WRSR instruction and the 8 bits of the Status Register are latched-in, the internal write cycle is then triggered by the rising edge of S. This rising edge of S must appear no later than the 16th clock cycle of the WRSR instruction of the Status Register content (it must not appear a 17th clock pulse before the rising edge of S), otherwise the internal write sequence is not performed. Read Operation The chip is firstselected by putting S low. The serial one byte read instruction is followed by a one byte
address (A7-A0), each bit being latched-in during the rising edge of the clock (C). Bit 3 (see Table 3) of the read instruction contains address bit A8 (most significant address bit). Then the data stored in the memory at the selected addressis shifted out on the Q output pin; each bit being shifted out during the falling edge of the clock (C). The data stored in the memory at the next address can be read in sequence by continuing to provide clock pulses. The byte address is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to 0h allowing the read cycle to be continued indefinitely. The read operation is terminated by deselecting the chip. The chip can be deselectedat anytime during data output. Any read attempt during a write cycle will be rejected and will deselect the chip.
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Figure 7. Write Enable Latch Sequence
S 0 C 1 2 3 4 5 6 7
D HIGH IMPEDANCE Q
AI01441
Figure 8. Byte Write Operation Sequence
S 0 C INSTRUCTION BYTE ADDRESS DATA BYTE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
HIGH IMPEDANCE Q
AI01442
Notes:
A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only active on ST95040.
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ST95040, ST95020, ST95010
Figure 9. Page Write Operation Sequence
S 0 C INSTRUCTION BYTE ADDRESS DATA BYTE 1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
D
A8
A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
7
S 10+8N 11+8N 12+8N 13+8N 14+8N 15+8N 9+8N
136
137
138
139
140
141 2
142 1
24 25 26 27 28 29 30 31 C DATA BYTE 2
8+8N
DATA BYTE N
DATA BYTE 16
D
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
0
Notes:
A8 = A7 = 0 on ST95010; A8 = 0 on ST95020; A8 is only active on ST95040.
Figure 10. RDSR: Read Status Register Sequence
S 0 C INSTRUCTION D STATUS REG. OUT HIGH IMPEDANCE Q 7 MSB
AI01444
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
6
5
4
3
2
1
0
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143
AI01443
ST95040, ST95020, ST95010
Figure 11. WRSR: Write Status Register Sequence
S 0 C INSTRUCTION STATUS REG. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
D HIGH IMPEDANCE Q
AI01445
Byte Write Operation Prior to any write attempt, the write enable latch must be set by issuing the WREN instruction. First the device is selected (S = low) and a serial WREN instruction byte is issued. Then the product is deselected by taking S high. After the WREN instruction byte is sent, the Memory will set the write enable latch and then remain in standby until it is deselected. Then the write state is entered by selecting the chip, issuing two bytes of instruction and address, and one byte of data. Chip Select (S) must remain low for the entire duration of the operation. The product must be deselectedjust after the eighth bit of data has been latched in. If not, the write process is cancelled. As soon as the product is deselected, the self-timed writecycle is initiated. While the write isin progress, the status register may be read to checkBP1, BP0, WEL and WIP. WIP is high during the self-timed write cycle. When the cycle is completed, the write enable latch is reset. Page Write Operation A maximum of 16 bytes of data may be written during one non-volatile write cycle. All 16 bytes
must reside on the same page. The page write mode is the same as the byte write mode except that instead of deselecting the device after the first byte of data, upto 15 additionalbytes can be shifted in prior to deselecting the chip. A page address begins with address xxxx 0000 and ends with xxxx 1111.If the address counter reaches xxxx 1111and the clock continues, the counter will roll over to the first address of the page (xxxx 0000) and overwrite any previously written data. The programming cycle will only start if the S transition occurs just after the eighth bit of data of a word is received. POWER ON STATE After a Power up the Memory is in the following state: - The device is in the low power standby state. - The chip is deselected. - The chip is not in hold condition. - The write enable latch is reset. - BP1 and BP0 are unchanged (non-volatile bits).
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ST95040, ST95020, ST95010
Figure 12. EEPROM and SPI Bus
D Q C MASTER CQD ST95xxx CS3 CS2 CS1 S CQD ST95xxx S CQD ST95xxx S
AI01446
DATA PROTECTION AND PROTOCOL SAFETY - All inputs are protected against noise, see Table 6. - Non valid S and HOLD transitions are not taken into account. - S must come high at the proper clock count in order to start a non-volatile write cycle (in the memory array or in the status register), that is the Chip Select S mustrise during the clock pulse following the introduction of a multiple of 8 bits. - Access to the memory array during non-volatile programming cycle is ignored; however, the programming cycle continues.
- Afterany of the operations WREN, WRDI, RDSR is completed, the chip enters a wait state and waits for a deselect. - The write enable latch is reset upon power-up. - The writeenable latch is resetwhen W is brought low. INITIAL DELIVERY STATE The device is delivered with the memory array in a fully erased state (all data set at all "1's" or FFh). The block protect bits are initialized to 00.
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ST95040, ST95020, ST95010
Table 5. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages Output Load 50ns 0.2VCC to 0.8VCC 0.3VCC to 0.7VCC CL = 100pF
0.2VCC 0.8VCC 0.7VCC 0.3VCC
AI00825
Figure 13. AC Testing Input Output Wavef.
Note that Output Hi-Z is defined as the point where data is no longer driven.
Table 6. Input Parameters (1) (TA = 25 C, f = 2 MHz )
Symbol C IN C IN tLPF Parameter Input Capacitance (D) Input Capacitance (other pins) Input Signal Pulse Width Filtered Out Min Max 8 6 10 Unit pF pF ns
Note: 1. Sampled only, not 100% tested.
Table 7. DC Characteristics (TA = 0 to 70C, -40 to 85C or -40 to 125C; VCC = 4.5V to 5.5V or 2.5V to 5.5V)
Symbol ILI ILO Parameter Input Leakage Current Output Leakage Current C = 0.1 VCC/0.9 VCC , @ 2 MHz, Q = Open C = 0.1 VCC/0.9 VCC , @ 2 MHz, Q = Open, Note 2 Supply Current (W series) C = 0.1 VCC/0.9 VCC , @ 1 MHz, VCC = 2.5V, Q = Open S = VCC, VIN = VSS or VCC Standby Current ICC1 Standby Current (W series) VIL VIH VOL (1) Input Low Voltage Input High Voltage Output Low Voltage Output Low Voltage (W series)
(1)
Test Condition
Min
Max 2 2 2 2
Unit A A mA mA
Supply Current ICC
1.5 50 50 25 - 0.3 0.7 VCC 0.3 VCC VCC + 1 0.4 0.4 0.4 VCC -0.6 VCC -0.6 VCC -0.3
mA A A A V V V V V V V V
S = VCC, VIN = VSS or VCC, Note 2 S = VCC, VIN = VSS or VCC, VCC = 2.5V
IOL = 2mA IOL = 2mA, Note 2 IOL = 1.5mA, VCC = 2.5V IOH = -2mA IOH = -2mA, Note 2
VOH
Output High Voltage Output High Voltage (W series)
IOH = -0.4mA, VCC = 2.5V
Notes: 1. The device meets output requirements for both TTL and CMOS standards. 2. Test performed at -40 to 125C temperature range, grade 3.
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ST95040, ST95020, ST95010
Table 8. AC Characteristics
ST95040 / 020 / 010 Symbol Alt Parameter VCC = 4.5V to 5.5V, TA = 0 to 70C, TA = -40 to 85C Min fC tSLCH tCHSL tCH (1) tCL(1) tCLCH tCHCL tDVCH tCHDX tDLDH tDHDL tHHCH tHLCH tCLHL tCLHH tCHSH tSHCH tSHSL tSHQZ tCLQV tCLQX tQLQH (2) tQHQL (2) tHHQX tHLQZ tW tCSH tDIS tV tHO tRO tFO tLZ tHZ tWP tHH tCLH tCLL tRC tFC tDSU tDH tRI tFI tHSU fC tCSS Clock Frequency S Active Setup Time S Not Active Hold Time Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Data In Setup Time Data In Hold Time Data In Rise Time Data In Fall Time HOLD Setup Time Clock Low Hold Time HOLD Hold Time Clock Low Set-up Time S Active Hold Time S Not Active Setup Time S Deselect Time Output Disable Time Clock Low to Output Valid Output Hold Time Output Rise Time Output Fall Time HOLD High to Output Low-Z HOLD Low to Output High-Z Write Cycle Time 0 100 100 100 130 10 100 90 80 100 200 100 200 150 240 0 100 100 100 130 10 50 50 1 1 100 90 80 100 200 100 200 150 300 0 200 200 200 200 10 D.C. 100 100 190 200 1 1 50 50 1 1 200 200 200 200 200 200 200 200 400 Max 2 VCC = 4.5V to 5.5V, TA = -40 to 125C Min D.C. 100 100 200 200 1 1 100 100 1 1 Max 2 VCC = 2.5V to 5.5V, TA = 0 to 70C, TA = -40 to 85C Min D.C. 200 200 400 400 1 1 Max 1 MHz ns ns ns ns s s ns ns s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms Unit
Notes: 1. tCH + tCL 1/fc 2. Value guaranteed by characterization, not 100% tested in production.
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ST95040, ST95020, ST95010
Figure 14. Serial Input Timing
tSHSL S tCHSL C tDVCH tCHDX D MSB IN tDLDH tDHDL tCLCH LSB IN tCHCL tSLCH tCHSH tSHCH
Q
HIGH IMPEDANCE
AI01447
Figure 15. Hold Timing
S tHLCH tCLHL C tCLHH tHLQZ Q tHHQX tHHCH
D
HOLD
AI01448
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ST95040, ST95020, ST95010
Figure 16. Output Timing
S tCH C tCLQV tCLQX Q tQLQH tQHQL D
ADDR.LSB IN
tCL
tSHQZ
LSB OUT
AI01449B
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ST95040, ST95020, ST95010
ORDERING INFORMATION SCHEME Example: ST95xx0 W M 6 TR
Density 04 02 01 4K (512 x 8) 2K (256 x 8) 1K (128 x 8) TR
Option Tape & Reel Packing
Data Strobe 0 Note 1
Operating Voltage blank 4.5V to 5.5V W 2.5V to 5.5V M B
Package PSDIP8 0.25 mm Frame SO8 150mils Width 3
Temperature Range 1 6
(2)
0 to 70 C -40 to 85 C -40 to 125 C
Notes: 1. Data In is strobed on rising edge of the clock (C) and Data Out is synchronized from the falling edge of the clock. 2. Temperature range on request only, 5V 10% only.
Devices are shipped from the factory with the memory content set at all "1's" (FFh). For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
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ST95040, ST95020, ST95010
PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame
Symb Typ A A1 A2 B B1 C D E E1 e1 eA eB L N CP 3.00 8 0.10 2.54 7.62 mm Min 3.90 0.49 3.30 0.36 1.15 0.20 9.20 - 6.00 - 7.80 Max 5.90 - 5.30 0.56 1.65 0.36 9.90 - 6.70 - - 10.00 3.80 0.118 8 0.004 0.100 0.300 Typ inches Min 0.154 0.019 0.130 0.014 0.045 0.008 0.362 - 0.236 - 0.307 Max 0.232 - 0.209 0.022 0.065 0.014 0.390 - 0.264 - - 0.394 0.150
A2 A1 B B1 D
N
A L eA eB C
e1
E1
1
E
PSDIP-a
Drawing is not to scale
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ST95040, ST95020, ST95010
SO8 - 8 lead Plastic Small Outline, 150 mils body width
Symb Typ A A1 B C D E e H h L N CP 1.27 mm Min 1.35 0.10 0.33 0.19 4.80 3.80 - 5.80 0.25 0.40 0 8 0.10 Max 1.75 0.25 0.51 0.25 5.00 4.00 - 6.20 0.50 0.90 8 0.050 Typ inches Min 0.053 0.004 0.013 0.007 0.189 0.150 - 0.228 0.010 0.016 0 8 0.004 Max 0.069 0.010 0.020 0.010 0.197 0.157 - 0.244 0.020 0.035 8
h x 45 A C B e D CP
N
E
1
H A1 L
SO-a
Drawing is not to scale
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ST95040, ST95020, ST95010
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1998 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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